LPC2930 NXP Semiconductors, LPC2930 Datasheet - Page 30

• Manufacturer Part Number: LPC2930
• Description: The LPC2930 combine an ARM968E-S CPU core with two integrated TCM blocksoperating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2930_3
Product data sheet
6.11.2.1 Functional description
6.11.2.2 Clock description
6.11.2 Watchdog timer
6.11.3 Timer
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.
The watchdog should be programmed with a time-out value and then periodically
restarted. When the watchdog times out, it generates a reset through the RGU.
To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled
via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing
to the clear-interrupt register.
Another way to prevent resets during debug mode is via the Pause feature of the
watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the watchdog timer control register is set.
The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains
a reset source register to identify the reset source when the device has gone through a
reset. See
The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE,
see
CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is
always on.
The LPC2930 contains six identical timers: four in the peripheral subsystem and two in the
Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral
base addresses. This section describes the four timers in the peripheral subsystem. Each
timer has four capture inputs and/or match outputs. Connection to device pins depends on
the configuration programmed into the port function-select registers. The two timers
located in the MSCSS have no external capture or match pins, but the memory map is
identical, see
function.
The key features are:
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Internal chip reset if not periodically triggered.
Timer counter register runs on always-on safe clock.
Optional interrupt generation on watchdog time-out.
Debug mode with disabling of reset.
Watchdog control register change-protected with key.
Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.
32-bit timer/counter with programmable 32-bit prescaler
Section
Section
6.6.2. The register interface towards the system bus is clocked by
Section
All information provided in this document is subject to legal disclaimers.
6.14.4.
6.13.6. One of these timers has an external input for a pause
Rev. 03 — 16 April 2010
ARM9 microcontroller with CAN, LIN, and USB
LPC2930
© NXP B.V. 2010. All rights reserved.
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