LPC2939 NXP Semiconductors, LPC2939 Datasheet - Page 27
![The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocksoperating at frequencies of up to 125 MHz, Full-speed USB 2](/photos/41/52/415298/sot459-1_3d_sml.gif)
LPC2939
Manufacturer Part Number
LPC2939
Description
The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocksoperating at frequencies of up to 125 MHz, Full-speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2939.pdf
(99 pages)
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NXP Semiconductors
LPC2939_3
Product data sheet
A timing diagram for writing to external memory is shown In
between wait state settings is indicated with arrows.
Fig 5.
Fig 6.
(1) BLS has the same timing as WE in configurations that use the byte lane enable signals to connect
WSTOEN = 3, WST1 = 6
Reading from external memory
WSTWEN = 3, WST2 = 7
to write enable (8 bit devices).
Writing to external memory
WE/BLS
CLK(SYS)
All information provided in this document is subject to legal disclaimers.
CLK(SYS)
BLS
OE
CS
CS
(1)
A
D
A
D
Rev. 03 — 7 April 2010
WSTOEN
WSTWEN
ARM9 microcontroller with CAN, LIN, and USB
WST1
WST2
Figure
002aae704
6. The relationship
002aae705
LPC2939
© NXP B.V. 2010. All rights reserved.
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