LPC2939 NXP Semiconductors, LPC2939 Datasheet - Page 74
![The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocksoperating at frequencies of up to 125 MHz, Full-speed USB 2](/photos/41/52/415298/sot459-1_3d_sml.gif)
LPC2939
Manufacturer Part Number
LPC2939
Description
The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocksoperating at frequencies of up to 125 MHz, Full-speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2939.pdf
(99 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2939FBD208
Manufacturer:
NXP
Quantity:
105 000
Company:
Part Number:
LPC2939FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
LPC2939FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
9. Dynamic characteristics
Table 36.
V
ground; positive currents flow into the IC; unless otherwise specified.
[1]
[2]
[3]
[4]
LPC2939_3
Product data sheet
Symbol
I/O pins
t
t
CLK_OUT pin
f
Internal clock
f
T
Low-power ring oscillator
f
t
Oscillator
f
t
PLL
f
f
t
t
Jitter specification for CAN
t
THL
TLH
clk
clk(sys)
ref(RO)
startup
i(osc)
startup
i(PLL)
o(PLL)
a(clk)
a(A)
jit(cc)(p-p)
DD(CORE)
clk(sys)
All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T
temperature on wafer level. Cased products are tested at T
test conditions to cover the specified temperature and power supply voltage range.
See
This parameter is not part of production testing or final testing, hence only a typical value is stated.
Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully
stable.
Table
= V
Dynamic characteristics
DD(OSC_PLL)
27.
9.1 Dynamic characteristics: I/O and CLK_OUT pins, internal clock,
Parameter
HIGH to LOW transition
time
LOW to HIGH transition
time
clock frequency
system clock frequency
system clock period
RO reference
frequency
start-up time
oscillator input
frequency
start-up time
PLL input frequency
PLL output frequency
clock access time
address access time
cycle to cycle jitter
(peak-to-peak value)
oscillators, PLL, and CAN
; V
DD(IO)
= 2.7 V to 3.6 V; V
All information provided in this document is subject to legal disclaimers.
Conditions
C
C
on pin CLK_OUT
at maximum frequency
maximum frequency is
the clock input of an
external clock source
applied to the
XIN_OSC pin
at maximum frequency
CCO; direct mode
on TXDCn pin
L
L
= 30 pF
= 30 pF
Rev. 03 — 7 April 2010
DDA(ADC3V3)
amb
= 25 C (final testing). Both pre-testing and final testing use correlated
= 3.0 V to 3.6 V; all voltages are measured with respect to
[1]
ARM9 microcontroller with CAN, LIN, and USB
[2]
[2]
[3]
[3]
[4]
[3]
Min
4
4
-
10
8
0.4
-
10
-
10
10
156
-
-
-
Typ
-
-
-
-
-
0.5
6
-
500
-
-
-
-
-
0.4
Max
13.8
13.8
40
125
100
0.6
-
100
-
25
160
320
63.4
60.3
1
LPC2939
© NXP B.V. 2010. All rights reserved.
amb
= 85 C ambient
Unit
ns
ns
MHz
MHz
ns
MHz
s
MHz
s
MHz
MHz
MHz
ns
ns
ns
74 of 99