P89LPC9321 NXP Semiconductors, P89LPC9321 Datasheet - Page 42

• Manufacturer Part Number: P89LPC9321
• Description: The P89LPC9321 is a single-chip microcontroller, available in low cost packages, basedon a high performance processor architecture that executes instructions in two to fourclocks, six times the rate of standard 80C51 devices
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9321
Product data sheet
7.26 Analog comparators
Two analog comparators are provided on the P89LPC9321. Input and output options
allow use of the comparators in a number of different configurations. Comparator
operation is such that the output is a logical one (which may be read in a register and/or
routed to a pin) when the positive input (one of two selectable inputs) is greater than the
negative input (selectable from a pin or an internal reference voltage). Otherwise the
output is a zero. Each comparator may be configured to cause an interrupt when the
output value changes.
The positive inputs of comparators could be amplified by Programmable Gain Amplifier 1
(PGA1) module. The PGA1 can supply gain factors of 2x, 4x, 8x, or 16x, eliminating the
need for external op-amps in the end application.
The overall connections to both comparators are shown in
function to V
When each comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 μs. The corresponding comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before the
interrupt is enabled in order to prevent an immediate interrupt service.
When a comparator is disabled the comparator’s output, COn, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will
cause an interrupt if the comparator interrupt is enabled. The user should therefore
disable the comparator interrupt prior to disabling the comparator. Additionally, the user
should clear the comparator flag, CMFn, after disabling the comparator.
Fig 18. SPI single master multiple slaves configuration
GENERATOR
8-BIT SHIFT
SPI CLOCK
REGISTER
DD
master
= 2.4 V.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2010
8-bit microcontroller with accelerated two-clock 80C51 core
MISO
MOSI
SPICLK
port
port
SPICLK
SPICLK
MISO
MOSI
MISO
MOSI
Figure
SS
SS
P89LPC9321
19. The comparators
8-BIT SHIFT
8-BIT SHIFT
REGISTER
REGISTER
© NXP B.V. 2010. All rights reserved.
slave
slave
002aaa903
42 of 71