STM32W108C8 STMicroelectronics, STM32W108C8 Datasheet - Page 101

• Manufacturer Part Number: STM32W108C8
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with 64-Kybte Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108C8

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch and breakpoint; data watchpoint and trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108C8
9.13
9.13.1
Table 67.
31
15
30
14
DMA channel registers
Serial DMA control register (SCx_DMACTRL)
Address offset: 0xC830 (SC1_DMACTRL) and 0xC030 (SC2_DMACTRL)
Reset value:
Serial DMA control register (SCx_DMACTRL)
Bit 5 SC_TXDMARST: Setting this bit resets the transmit DMA. The bit clears automatically.
Bit 4 SC_RXDMARST: Setting this bit resets the receive DMA. The bit clears automatically.
Bit 3 SC_TXLODB: Setting this bit loads DMA transmit buffer B addresses and allows the DMA
Bit 2 SC_TXLODA: Setting this bit loads DMA transmit buffer A addresses and allows the DMA
Bit 1 SC_RXLODB: Setting this bit loads DMA receive buffer B addresses and allows the DMA
Bit 0 SC_RXLODA: Setting this bit loads DMA receive buffer A addresses and allows the DMA
29
13
controller to start processing transmit buffer B. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
controller to start processing transmit buffer A. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
controller to start processing receive buffer B. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
controller to start processing receive buffer A. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
28
12
27
11
Reserved
0x0000 0000
26
10
25
9
Doc ID 018587 Rev 2
24
8
Reserved
23
7
22
6
DMARS
SC_TX
21
T
w
5
XDMA
SC_R
RST
20
w
4
SC_TX
LODB
19
rw
3
SC_TX
LODA
Serial interfaces
18
rw
2
SC_RX
LODB
17
rw
1
100/215
SC_RX
LODA
16
rw
0