STM32W108C8 STMicroelectronics, STM32W108C8 Datasheet - Page 89

• Manufacturer Part Number: STM32W108C8
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with 64-Kybte Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108C8

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch and breakpoint; data watchpoint and trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108C8
9.6.5
9.7
Note:
offset is 4 characters ahead of the actual overflow at the input to the receive FIFO. Two
conditions will clear the error indication: setting the appropriate SC_RXDMARST bit in the
SC1_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded.
Interrupts
UART interrupts are generated on the following events:
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To enable CPU interrupts, set the desired interrupt bits in the second level INT_SCxCFG
register, and enable the top level SCx interrupt in the NVIC by writing the INT_SCx bit in the
INT_CFGSET register.
Direct memory access (DMA) channels
The STM32W108C8 serial DMA channels enable efficient, high-speed operation of the SPI
and UART controllers by reducing the load on the CPU as well as decreasing the frequency
of interrupts that it must service. The transmit and receive DMA channels can transfer data
between the transmit and receive FIFOs and the DMA buffers in main memory as quickly as
it can be transmitted or received. Once software defines, configures, and activates the DMA,
it only needs to handle an interrupt when a transmit buffer has been emptied or a receive
buffer has been filled. The DMA channels each support two memory buffers, labeled A and
B, and can alternate ("ping-pong") between them automatically to allow continuous
communication without critical interrupt timing.
DMA memory buffer terminology:
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To use a DMA channel, software should follow these steps:
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Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE,
either the 0 to 1 transition or the high level of SC1_UARTTXIDLE)
Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0
to 1 transition or the high level of SC1_UARTTXFREE)
Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either
the 0 to 1 transition or the high level of SC1_UARTRXVAL)
Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)
Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)
Character received with parity error
Character received with frame error
Character received and lost when receive FIFO was full (receive overrun error)
load - make a buffer available for the DMA channel to use
pending - a buffer loaded but not yet active
active - the buffer that will be used for the next DMA transfer
unload - DMA channel action when it has finished with a buffer
idle - a buffer that has not been loaded, or has been unloaded
Reset the DMA channel by setting the SC_TXDMARST (or SC_RXDMARST) bit in the
SCx_DMACTRL register.
Set up the DMA buffers. The two DMA buffers, A and B, are defined by writing the start
address to SCx_TXBEGA/B (or SCx_RXBEGA/B) and the (inclusive) end address to
SCx_TXENDA/B (or SCx_RXENDA/B). Note that DMA buffers must be in RAM.
Configure and initialize SCx for the desired operating mode.
Enable second level interrupts triggered when DMA buffers unload by setting the
INT_SCTXULDA/B (or INT_SCRXULDA/B) bits in the INT_SCxFLAG register.
Doc ID 018587 Rev 2
Serial interfaces
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