STM32W108C8 STMicroelectronics, STM32W108C8 Datasheet - Page 82

• Manufacturer Part Number: STM32W108C8
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with 64-Kybte Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108C8

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch and breakpoint; data watchpoint and trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

Serial interfaces
9.5.1
Note:
9.5.2
81/215
The I
●
●
Table 45
pins are configured as open-drain outputs, they require external pull-up resistors.
Table 45.
Setup and configuration
The I
operates only in master mode and supports both Standard (100 kbps) and Fast (400 kbps)
I
supported.
The I
generator. SCL is produced by dividing down 12 MHz according to this equation:
EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the
SCx_RATELIN register.
Standard-Mode I
Table 46.
At 400 kbps, the Philips I
1.3 µs, but on the STM32W108 it is 1.25 µs. If a slave device requires strict compliance with
SCL timing, the clock rate must be lowered to 375 kbps.
Constructing frames
The I
SC_TWISTART, SC_TWISTOP, SC_TWISEND, and SC_TWIRECV bits in the
SCx_TWICTRL1 registers.
2
Direction
GPIO configuration
SC1 pin
SC2 pin
C modes. Address arbitration is not implemented, so multiple master applications are not
SDA (Serial Data) - bidirectional serial data
SCL (Serial Clock) - bidirectional serial clock
2
2
2
2
C master controller uses just two signals:
C controller is enabled by writing 3 to the SCx_MODE register. The I
C master controller's serial clock (SCL) is produced by a programmable clock
C master controller supports generating various frame segments by means of the
lists the GPIO pins used by the SC1 and SC2 I
Parameter
Clock rate
100 kbps
375 kbps
400 kbps
I
I
2
2
C Master GPIO Usage
C clock rate programming
2
C (100 kbps) and Fast-Mode I
I2C clock rate programming on page 81
2
C Bus specification requires the minimum low period of SCL to be
Figure 47
Doc ID 018587 Rev 2
Rate
summarizes these frames.
Alternate Output
=
SCx_RATELIN
Input / Output
(open drain)
---------------------------------------- -
(
LIN
SDA
PB1
PA1
14
15
14
12MHz
+
2
C (400 kbps) operation.
1
)x2
2
EXP
C master controllers. Because the
shows the rate settings for
Alternate Output
SCx_RATEEXP
Input / Output
(open drain)
SCL
PB2
PA2
2
STM32W108C8
C controller
3
1
1