ST72521AR9 STMicroelectronics, ST72521AR9 Datasheet - Page 149

• Manufacturer Part Number: ST72521AR9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72521AR9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

CONTROLLER AREA NETWORK (Cont’d)
Software Work-around - Devices without Hard-
ware Fix:
To implement a transmission abort under safe
conditions, any reset of the LOCK bit during the
critical window (2 bit times) must be avoided. Two
different cases have to be considered, either the
pCAN enters standby mode after the abort, or the
abort is performed and pCAN keeps running.
Abort followed by STANDBY mode (RUN=0)
In this case, aborting the pending transmissions
can safely be done by first entering STANDBY
mode and then releasing the transmit buffers.
STANDBY mode is entered by resetting the RUN
bit in the CSR register and once the current trans-
mission attempt, even if it fails due to error or lost
arbitration, has been performed, pCAN enters
STANDBY mode (RUN=0). Once in STANDBY
mode the application can abort all pending trans-
missions by resetting the corresponding LOCK bit.
_asm("SIM\n");
CANCSR |= NRTX;
while(!(CANBCSR & BUSY) &&// Wait till BUSY bit is set
while( CANBCSR & BUSY ); // Wait till BUSY bit is reset (falling edge)
if( CANBCSR & RDY )
{ // transmission still pending -> must be aborted
}
else
{ // No more abort required as RDY bit already reset
}
CANBCSR &= ~LOCK; //Arbitration lost => cancel transmission safel
while( CANBCSR & RDY );// Wait for unlock confirmed
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n");
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n"); // Enable interrupts
(CANBCSR & RDY) ); // or transmission done
// Mask interrupts
// Set non automatic retransmission bit
Abort while staying in RUN mode (RUN=1)
Contrary to the STANDBY case described previ-
ously, in the RUN case the application has to han-
dle the error or arbitration lost conditions. In case
of transmission errors, causing the frame to be
transmitted again and again, the application must
set the NRTX bit in the CSR register. This will
cause pCAN to abort the transmission at the end
of the current attempt.
In case of arbitration lost, setting the NRTX bit
does not abort the transmission, therefore the ap-
plication must reset the LOCK bit to abort the
transmission. To avoid resetting the LOCK bit dur-
ing the critical time window, leading to the problem
described at the start of this section, the applica-
tion must monitor the BUSY bit in the BCSR regis-
ter and reset the LOCK bit just after the falling
edge of the BUSY bit. The time between the falling
edge of the BUSY bit and the SOF of the next
transmission attempt is in any case long enough to
guarantee that the LOCK bit is reset before the
critical time window.
The “C” code sequence below shows the software
work-around for both the error and arbitration lost
cases.
ST72F521, ST72521B
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