ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 58

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

Power saving modes
8.4.2
58/201
Figure 23. Active halt mode flow-chart
1. Peripheral clocked with an external clock source can still be active
2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from active halt mode (such as
3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
Halt mode
The halt mode is the lowest power consumption mode of the MCU. It is entered by executing
the ‘HALT’ instruction when the OIE bit of the main clock controller status register (MCCSR)
is cleared (see
(MCC/RTC) on page 73
The MCU can exit halt mode on reception of either a specific interrupt (see
Interrupt mapping on page
interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is
used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see
When entering halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
external interrupt). Refer to
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
Section 10.2: Main clock controller with real-time clock and beeper
for more details on the MCCSR register).
N
Table 15: Interrupt mapping on page 53
53) or a reset. When exiting halt mode by means of a reset or an
(MCCSR.OIE = 1)
HALT instruction
Interrupt
Y
(2)
Oscillator
Peripherals
CPU
I[1:0] bits
Oscillator
Peripherals
CPU
I[1:0] bits
Oscillator
Peripherals
CPU
I[1:0] bits
N
256 OR 4096 CPU clock
Fetch reset vector or
service interrupt
cycle delay
(1)
Y
Reset
for more details.
XX
XX
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
(3)
(3)
ST7232Axx-Auto
Figure
Table 15:
25).