ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 89

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
One pulse mode
One pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the input capture1 function and the output compare1 function.
Procedure
To use one pulse mode:
1.
2.
3.
Figure 42. One pulse mode sequence
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1.
2.
Load the OC1R register with the value corresponding to the length of the pulse using
the appropriate formula below according to the timer clock source used
Select the following in the CR1 register:
–
–
–
Select the following in the CR2 register:
–
–
–
Reading the SR register while the ICFi bit is set
Accessing (reading or writing) the ICiLR register
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input)
Set the OC1E bit (the OCMP1 pin is then dedicated to the output compare 1
function)
Set the OPM bit
Select the timer clock CC[1:0] (see
When event occurs
counter = OCIR
on ICAP1
When
One pulse mode cycle
Table 36: CR2 register
Counter is reset to FFFCh
OCMP1 = OLVL2
OCMP1 = OLVL1
ICR1 = counter
ICF1 bit is set
description)
On-chip peripherals
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