ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 116

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

On-chip peripherals
11.4.5
11.4.6
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6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
8. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
9. EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
10. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
11. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
Low power modes
Table 42.
Interrupts
Figure 58. Event flags and interrupt generation
Table 43.
1. The I
Mode
Wait
Halt
subsequent EV4 is not seen.
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is
reset (RIM instruction).
Arbitration lost event (Multimaster configuration)
*
EVF can also be set by EV6 or an error from the SR2 register.
STOPF
ADD10
10-bit address sent event (Master mode)
Start bit generation event (Master mode)
BERR
ARLO
ADSL
2
Address matched event (Slave mode)
C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
*
BTF
Stop detection event (Slave mode)
SB
AF
In Halt mode, the I
I
2
C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Effect of low power modes on the I
Description of interrupt events
Acknowledge failure event
End of byte transfer event
Interrupt event
Bus error event
I
2
2
C interrupts cause the device to exit from Wait mode.
C interface is inactive and does not acknowledge data on the bus. The
Doc ID 13562 Rev 3
(1)
No effect on I
ITE
I
2
Halt mode” capability.
C registers are frozen.
Description
2
2
C interface
C interface.
ADD10
STOPF
BERR
Event
ARLO
ADSL
BTF
flag
SB
AF
control
Enable
ITE
bit
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ST7LITE49M
from
Exit
Halt
No
No
No
No
No
No
No
No