ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 19

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
Table 3.
1. Legend: x=undefined, R/W=read/write.
2. For a description of the debug module registers, see ICC protocol reference manual.
Address
003Eh to
0052h to
003Ah
003Bh
003Ch
003Dh
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
006Ah
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
0047h
0048h
0049h
0050h
0051h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
Hardware register map
Clock and
EEPROM
Controller
FLASH
Block
DM
Clock
WDG
MCC
AWU
reset
ADC
I2C
(2)
Register label
CKCNTCSR
AVDTHCR
AWUCSR
ADCCSR
ADCDRH
I2COAR1
I2COAR2
ADCDRL
DMBK1H
DMBK2H
DMBK1L
DMBK2L
WDGCR
I2CCCR
MCCSR
AWUPR
DMCR2
I2CSR1
I2CSR2
EECSR
SICSR
DMCR
I2CCR
I2CDR
RCCR
DMSR
FCSR
(1)
(continued)
System integrity control/status register
Data EEPROM control/status register
AVD threshold selection register / RC
Main Clock Control/Status register
Doc ID 13562 Rev 3
Clock controller status register
DM breakpoint register 1 High
DM breakpoint register 2 High
DM breakpoint register 1 Low
DM breakpoint register 2 Low
RC oscillator control register
Flash control/status register
AWU control/status register
I
I
Reserved area (10 bytes)
Reserved area (18 bytes)
A/D control status register
Watchdog control register
2
2
I
Reserved area (1 byte)
Reserved area (1 byte)
2
C own address register 1
C own address register 2
A/D data register high
AWU Preload register
C clock control register
DM control register 2
I
I
DM control register
I
2
2
DM status register
2
C status register 1
C status register 2
I
Register name
C control register
2
C data register
prescaler
Register and memory mapping
Reset status
011x 0x00b
7Fh
00h
00h
00h
FFh
FFh
00h
xxh
0xh
00h
00h
00h
00h
00h
00h
00h
00h
00h
09h
00h
00h
00h
00h
00h
40h
00h
Read Only
Read only
Read only
Remarks
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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