ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 80

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

On-chip peripherals
11.2.3
80/188
Functional description
PWM mode
This mode allows up to four pulse width modulated signals to be generated on the PWMx
output pins.
●
●
PWM frequency
The four PWM signals can have the same frequency (f
frequencies. This is selected by the ENCNTR2 bit which enables Single timer or Dual
timer mode (see
period and the ATR register value. In Dual timer mode, PWM2 and PWM3 can be
generated with a different frequency controlled by CNTR2 and ATR2.
Following the above formula, if f
2 MHz (ATR register value = 4094), and the minimum value is 1 kHz (ATR register
value = 0).
The maximum value of ATR is 4094 because it must be lower than the DC4R value
which must be 4095 in this case.
To update the DCRx registers at 32 MHz, the following precautions must be taken:
–
–
Duty cycle
The duty cycle is selected by programming the DCRx registers. These are preload
registers. The DCRx values are transferred in Active duty cycle registers after an
overflow event if the corresponding transfer bit (TRANx bit) is set.
The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit
controls the PWMx outputs driven by counter 2.
PWM generation and output compare are done by comparing these active DCRx
values with the counter.
The maximum available resolution for the PWMx duty cycle is:
where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can
be obtained by changing the polarity.
At reset, the counter starts counting from 0.
When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are
transferred to the active Duty Cycle registers and the PWMx signals are set to a high
level. When the upcounter matches the active DCRx value the PWMx signals are set to
a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active
DCRx register must be greater than the contents of the ATR register.
If the PWM frequency is < 1 MHz and the TRANx bit is set asynchronously, it
should be set twice after a write to the DCRx registers.
If the PWM frequency is > 1 MHz, the TRANx bit should be set along with
FORCEx bit with the same instruction (use a load instruction and not 2 bset
instructions).
Figure 37
f
PWM
Doc ID 13562 Rev 3
Resolution
and
=
Figure
COUNTER
f
COUNTER
=
38). The frequency is controlled by the counter
1
equals 4 MHz
⁄
⁄
(
4096 ATR
(
4096 ATR
–
–
PWM
,
)
the maximum value of f
)
) or can have two different
ST7LITE49M
PWM
is