ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 122

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ST7LITE49M

Manufacturer Part Number
ST7LITE49M
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LITE49M

4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance
10k write/erase cycles guaranteed Data retention
128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
A/d Converter
10 input channels

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On-chip peripherals
Note:
Note:
122/188
If a bus error occurs, a Stop or a repeated Start condition should be generated by the
Master to re-synchronize communication, get the transmission acknowledged and the bus
released for further communication
Bit 0 = GCAL General Call bit (slave mode).
I
Reset value: 0000 0000 (00h)
Bit 7 = FM/SM Fast/Standard I
Bits 6:0 = CC[6:0] 7-bit clock divider bits
The programmed F
I
Reset value: 0000 0000 (00h)
Bits 7:0 = D[7:0] 8-bit data register
2
2
C clock control register (I2CCCR)
C data register (I2CDR)
FM/SM
D7
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the
interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
This bit is set and cleared by software. It is not cleared when the interface is disabled
(PE=0).
0: Standard I
1: Fast I
These bits select the speed of the bus (F
cleared when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for the table of values.
These bits contain the byte to be received or transmitted on the bus.
7
7
Transmitter mode: byte transmission start automatically when the software writes
in the DR register.
Receiver mode: the first data byte is received automatically in the DR register
using the least significant bit of the address. Then, the following data bytes are
received one by one after reading the DR register.
2
C mode
CC6
D6
2
C mode
SCL
assumes no load on SCL and SDA lines.
CC5
D5
2
Doc ID 13562 Rev 3
C mode bit
CC4
D4
Read / Write
Read / Write
SCL
) depending on the I
CC3
D3
CC2
D2
2
C mode. They are not
CC1
D1
ST7LITE49M
CC0
D0
0
0

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