ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 188

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

LINSCI serial communication interface (LIN master/slave)
15.10.5
15.10.6
Caution:
15.10.7
188/279
LIN divider registers
LDIV is coded using the two registers LPR and LPFR. In LIN slave mode, the LPR register is
accessible at the address of the SCIBRR register and the LPFR register is accessible at the
address of the SCIETPR register.
LIN prescaler register (LPR)
Read/ write
Reset value: 0000 0000 (00h)
LPR[7:0] LIN Prescaler (mantissa of LDIV)
These 8 bits define the value of the mantissa of the LIN Divider (LDIV):
Table 67.
LPR and LPFR registers have different meanings when reading or writing to them.
Consequently bit manipulation instructions (BRES or BSET) should never be used to modify
the LPR[7:0] bits, or the LPFR[3:0] bits.
LIN prescaler fraction register (LPFR)
Read/ write
Reset value: 0000 0000 (00h)
Bits 7:4 = Reserved.
Bits 3:0 = LPFR[3:0] Fraction of LDIV
These 4 bits define the fraction of the LIN Divider (LDIV):
LPR7
7
7
0
LPR[7:0]
FEh
FFh
00h
01h
LDIV mantissa
...
LPR6
0
LPR5
0
Doc ID 12468 Rev 3
LPR4
0
Rounded mantissa (LDIV)
LPFR3
LPR3
SCI clock disabled
254
255
...
1
LPFR2
LPR2
LPFR1
LPR1
ST72361xx-Auto
LPFR0
LPR0
0
0