ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 274

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Important notes
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Occurrence
The occurrence of the problem is random and proportional to the baud rate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
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LIN mode
If the LINE bit in the SCICR3 is set and the M bit in the SCICR1 register is reset, the LINSCI
is in LIN master mode. A single break character is sent by setting and resetting the SBK bit
in the SCICR2 register. In some cases, the break character may have a longer duration than
expected:
●
Occurrence
The occurrence of the problem is random and proportional to the baud rate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
Analysis
The LIN protocol specifies a minimum of 13 bits for the break duration, but there is no
maximum value. Nevertheless, the maximum length of the header is specified as
(14 + 10 + 10 + 1) x 1.4 = 49 bits. This is composed of:
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Every LIN frame starts with a break character. Adding an idle character increases the length
of each header by 10 bits. When the problem occurs, the header length is increased by 11
bits and becomes ((14 + 11) + 10 + 10 + 1) = 45 bits.
To conclude, the problem is not always critical for LIN communication if the software keeps
the time between the sync field and the ID smaller than 4 bits, that is, 208µs at 19200 baud.
The workaround is the same as for SCI mode but considering the low probability of
occurrence (1%), it may be better to keep the break generation sequence as it is.
Disable interrupts
Reset and set TE (IDLE request)
Set and reset SBK (Break Request)
Re-enable interrupts
24 bits instead of 13 bits
the synch break field (14 bits)
the synch field (10 bits)
the identifier field (10 bits)
CPU
CPU
Doc ID 12468 Rev 3
= 8 MHz and SCIBRR = 0xC9), the wrong break duration
= 8 MHz and SCIBRR = 0xC9), the wrong break duration
ST72361xx-Auto