73S1209F Maxim, 73S1209F Datasheet - Page 12

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit in the
2. Write pattern 0xAA to
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to
2. Write pattern 0x55 to
The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The
memory address such that bit 7:1 of the
Bit 0 of the PGADDR is not used and is ignored. The MPU may write to the flash memory. This is one of
the non-volatile storage options available to the user. The
write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM
writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows
the location and description of the 73S1209F flash-specific SFRs.
12
Any flash modifications must set the CPUCLK to operate at 3.6923 MHz
before any flash memory operations are executed to insure the proper timing when modifying the
flash memory.
ERASE
ERASE
PGADDR
(SFR address 0x94)
(SFR address 0x94).
PGADDR
(SFR address 0xB7[7:1])
FLSHCTL
corresponds to bit 15:9 of the flash memory address.
PGADDR
register (SFR address 0xB2[1]).
FLSHCTL
denotes the upper seven bits of the flash
SFR bit FLSH_PWE (flash program
(MPUCLKCtl
= 0x0C)
Rev. 1.2