73S1209F Maxim, 73S1209F Datasheet - Page 86

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

This register is used to monitor reception of data from the smart card.
STX Data Register (STXData): 0xFE07
MSB
SRX Control/Status Register (SRXCtl): 0xFE08
86
SRXCtl.7
SRXCtl.6
SRXCtl.5
SRXCtl.4
SRXCtl.3
SRXCtl.2
SRXCtl.1
SRXCtl.0
STXDAT.7
STXData.7
STXData.6
STXData.5
STXData.4
STXData.3
STXData.2
STXData.1
STXData.0
Bit
Bit
MSB
BIT9DAT
CRCERR
RXOVRR
PARITYE
BIT9DAT
RXEMTY
LASTRX
RXFULL
Symbol
STXDAT.6
Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by
the hardware and sent to the selected smart card. When the MPU reads this register,
the byte pointer is changed to effectively “read out” the data. Thus, two reads will
always result in an “empty” FIFO condition. The contents of the FIFO registers are not
cleared, but will be overwritten by writes.
–
–
Bit 9 Data – When in sync mode and with MODE9/8B set, this bit will contain
the data on IO (or SIO) pin that was sampled on the ninth CLK (or SCLK) rising
edge. This is used to read data in synchronous 9-bit formats.
Last RX Byte – User sets this bit during the reception of the last byte. When
byte is received and this bit is set, logic checks CRC to match 0x1D0F (T=1
mode) or LRC to match 00h (T=1 mode), otherwise a CRC or LRC error is
asserted.
(Read only) 1 = CRC (or LRC) error has been detected.
(Read only) RX FIFO is full. Status bit to indicate RX FIFO is full.
(Read only) RX FIFO is empty. This is only a status bit and does not generate
a RX interrupt.
RX Overrun – (Read Only) Asserted when a receive-over-run condition has
occurred. An over-run is defined as a byte was received from the smart card
when the RX FIFO was full. Invalid data may be in the receive FIFO. Firmware
should take appropriate action. Cleared when read. Additional writes to the
RX FIFO are discarded when a RXOVRR occurs until the overrun condition is
cleared. Will generate RXERR interrupt.
Parity Error – (Read only) 1 = The logic detected a parity error on incoming
data from the smart card. Cleared when read. Will generate RXERR interrupt.
STXDAT.5
LASTRX
Table 80: The STXData Register
Table 81: The SRXCtl Register
STXDAT.4
0x00
CRCERR
0x00
STXDAT.3
Function
RXFULL
Function
STXDAT.2
RXEMTY
STXDAT.1
RXOVRR PARITYE
STXDAT.0
Rev. 1.2
LSB
LSB