73S1209F Maxim, 73S1209F Datasheet - Page 30

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

Miscellaneous Control Register 1 (MISCtl1): 0xFFF2
Master Clock Control Register (MCLKCtl): 0x8F
*Note: The HSOEN bit should never be set under normal circumstances. Power down control should
only be initiated via use of the PWRDN bit in MISCtl0.
30
MISCtl1.7
MISCtl1.6
MISCtl1.5
MISCtl1.4
MISCtl1.3
MISCtl1.2
MISCtl1.1
MISCtl1.0
MCLKCtl.7
MCLKCtl.6
MCLKCtl.5
MCLKCtl.4
MCLKCtl.3
MCLKCtl.2
MCLKCtl.1
MCLKCtl.0
Bit
Bit
MSB
MSB
HSOEN
Symbol
FLSH66
FRPEN
–
HSOEN*
Symbol
MCT.2
MCT.1
MCT.0
KBEN
SCEN
–
–
–
–
–
–
–
–
KBEN
–
Flash Read Pulse enable (low). If FRPEN=1, the Flash Read signal is
passed through with no change. When FRPEN=0, a one-shot circuit that
shortens the Flash Read signal is enabled to save power. The Flash Read
pulse will shorten to 40 or 66ns (approximate based on the setting of the
FLSH66 bit) in duration, regardless of the MPU clock rate. For MPU clock
frequencies greater than 10MHz, this bit should be set high.
When high, creates a 66ns Flash read pulse, otherwise creates a 40ns read
pulse when FRPEN is set.
High-speed oscillator enable. When set = 1, disables the high-speed
crystal oscillator and VCO/PLL system. This bit is not changed when
the PWRDN bit is set but the oscillator/VCO/PLL is disabled.
1 = Disable the keypad logic clock. This bit is not changed in PWRDN
mode but the function is disabled.
1 = Disable the smart card logic clock. This bit is not changed in
PWRDN mode but the function is disabled. Interrupt logic for card
insertion/removal remains operable even with smart card clock
disabled.
This value determines the ratio of the VCO frequency (MCLK) to the
high-speed crystal oscillator frequency such that:
MCLK=(MCount*2 + 4)*Fxtal. The default value is MCount= 2h such
that MCLK = (2*2 + 4)*12.00MHz = 96MHz.
SCEN
FRPEN
Table 17: The MCLKCtl Register
Table 16: The MISCtl1 Register
FLSH66
–
0x0A
–
0x10
–
Function
Function
MCT.2
–
MCT.1
–
MCT.0
LSB
–
LSB
Rev. 1.2