73S1209F Maxim, 73S1209F Datasheet - Page 46

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

Timer/Counter Control Register (TCON): 0x88
1.7.6
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles.
After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a
16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once
the watchdog starts, it cannot be stopped unless the internal reset signal becomes active.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register
enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6
in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing
the state of the WDT timer.
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request
signal from becoming active. This requirement imposes an obligation on the programmer to issue two
instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay
allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has
not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of
the
46
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
WDTREL
Bit
WD Timer (Software Watchdog Timer)
MSB
register and WDT is automatically reset.
TF1
Symbol
TR1
TR0
TF1
TF0
IE1
IT1
IE0
IT0
TR1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
Timer 1 Run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This
flag can be cleared by software and is automatically cleared when an
interrupt is processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
External Interrupt 1 edge flag.
External interrupt 1 type control bit.
External Interrupt 0 edge flag.
External Interrupt 0 type control bit.
TF0
Table 43: The TCON Register
TR0
0x00
IE1
Function
IT1
IE0
IT0
LSB
Rev. 1.2