73S1209F Maxim, 73S1209F Datasheet - Page 27

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

DS_1209F_004
1.7.2
The 73S1209F contains circuitry to disable portions of the device and place it into lower power standby
modes. This is accomplished by either shutting off the power or disabling the clock going to the block.
The miscellaneous control registers MISCtl0,
provide control over the power modes. There is also a device power down mode that will stop the core,
clock subsystem and the peripherals connected to it. The PWRDN bit in
73S1209F for power down and disable all clocks. The power down mode should only be initiated by
setting the PWRDN bit in the
registers. Figure 5 shows how the PWRDN bit controls the various functions that comprise power down
state.
state.
When the PWRDN bit is set, the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the
program to set the STOP bit in the
core before the analog circuits shut down (high speed oscillator, VCO/PLL, voltage reference and bias
circuitry, etc.). The PDMUX bit in SFR
configure the wake up interrupt logic. The power down mode is de-asserted by any of the interrupts
connected to external interrupts 0, 4 and 5 (external USR[0:7], smart card and Keypad). These interrupt
sources are OR’ed together and routed through some delay logic into INT0 to provide this functionality.
The interrupt will turn on the power to all sections that were shut off and start the clock subsystem. After
the clock subsystem clocks start running, the MPUCLK begins to clock a 512 count delay counter. When
the counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 6
shows the detailed logic for waking up the 73S1209F from a power down state using these specific
interrupt sources. Figure 7 shows the timing associated with the power down mode.
Rev. 1.2
Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the
PWRDN bit to the assertion of the PWRDN Signal (32 MPU clocks) Refer to the Power Down sequence diagram.
the names of the control bits.
Power Control Modes
These are the registers and
SCVCCCtl - SCPRDN
MCLCKCtl - HOSEN
Figure 5 shows how the PWRDN bit controls the various functions that comprise power down
VDDFCtl - VDDFEN
MISCtl0 - PWRDN
ACOMP - CMPEN
MISCtl1 - FRPEN
MISCtl0
PWRDN Signal
PCON
Figure 5: Power-Down Control
register and not by manipulating individual control bits in various
INT5Ctl
register. This delay will enable the program to properly halt the
MISCtl1
should be set prior to setting the PWRDN bit in order to
+
+
+
+
+
and the Master Clock Control register (MCLKCtl)
reference and bias
Smart Card Power
Analog functions
Flash Read Pulse
High Speed OSC
one-shot circuit
block references.
circuits, etc.)
These are the
(VCO, PLL,
VDDFAULT
COMPARE
ANALOG
MISCtl0
will setup the
73S1209F Data Sheet
27