PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 193

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
J0Z0INCEN
TRACEEN
TSLDEN
TLDEN
APSEN
LREIEN
The J0 and Z0 increment enable (J0Z0INCEN) bit controls the insertion of an incremental
pattern in the section trace and Z0 growth bytes. When J0ZOINCEN is set to logic 1, the
corresponding STS-1/STM-0 path # is inserted in the J0 and Z0 bytes according to the
priority of Table 4. When J0Z0INCEN is set to logic 0, no incremental pattern is inserted.
For normal operation, the J0Z0INCEN bits in the TRMP Aux2 Configuration register, the
TRMP Aux3 Configuration register and the TRMP Aux4 Configuration register must be set to
the same value as the J0Z0INCEN bit.
The section trace enable (TRACEEN) bit controls the insertion of section trace in the data
stream. When TRACEEN is set to logic 1, the section trace from the Section TTTP block is
inserted in the J0 byte of STS-1/STM-0 #1 according to the priority of Table 4. When
TRACEEN is set to logic 0, the section trace from the J0[7:0] input port is not inserted.
The TSLD enable (TSLDEN) bit controls the insertion of section or line DCC in the data
stream. When TSLDEN is set to logic 1, the S/UNI-2488 inserts all ones or all zeros as
selected using the TSLD_VAL bit in the S/UNI-2488 Diagnostics register (000EH) into the
D1-D3 bytes or D4-D12 bytes of STS-1/STM-0 #1 according to the priority of Table 4.
When TSLDEN is set to logic 0, the section or line DCC is not inserted.
The TLD enable (TLDEN) bit controls the insertion of line DCC in the data stream. When
TLDEN is set to logic 1, the S/UNI-2488 inserts all ones or all zeros as selected using the
TLD_VAL bit in the S/UNI-2488 Diagnostics register (000EH) into in the D4-D12 bytes of
STS-1/STM-0 #1 according to the priority of Table 4. When TLDEN is set to logic 0, line
DCC is not inserted.
The APS enable (APSEN) bit controls the insertion of automatic protection switching in the
data stream. When APSEN is set to logic 1, the APS bytes from the RRMP are inserted in the
K1/K2 bytes of STS-1/STM-0 #1 according to the priority of Table 4. When APSEN is set to
logic 0, the APS bytes from the RRMP are not inserted.
The functionality of the LREIEN register bit has been replaced with the TREIINS register bit
in register 0903H. LREIEN must be left in its default state of logic 1 for proper operation.
S/UNI-2488 Telecom Standard Product Datasheet
Released
193