PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 459

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0843H: R8TD APS1 Analog Control 1
Register 084BH: R8TD APS2 Analog Control 1
Register 0853H: R8TD APS3 Analog Control 1
Register 085BH: R8TD APS4 Analog Control 1
This register controls internal analog functions. This register should be written to 0xcc34 for
normal operation.
Reserved
Reserved1
DRU_CTRL[3:0]
A_RSTB
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Reserved bits, must be set to the indicated default value for correct operation.
The Reserved1 bit must be set to logic 1 for proper operation.
The DRU_CTRL[3:0] bits control the DRU CTRL[3:0] inputs. The DRU_CTRL[3:0] bits
need to be set to ‘b1101 following a reset for correct operation of the S/UNI-2488.
The A_RSTB bit is a soft-reset for the Data Recovery Unit Analog block. Setting A_RSTB to
logic 0 will reset the block. A_RSTB should be set to logic 0 to conserve power consumption
for applications not using the APS port.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Reserved
DRU_ENB
RX_ENB
Reserved
A_RSTB
Reserved
Reserved
Reserved
Reserved
DRU_CTRL[3]
DRU_CTRL[2]
DRU_CTRL[1]
DRU_CTRL[0]
Reserved
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
X
Released
459