PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 435

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
RWB
BUSY
The active high read and active low write (RWB) bit selects if the current access to the
internal register is an indirect read or an indirect write. Writing to the Indirect Address
Register initiates an access to the internal register. When RWB is set to logic 1, an indirect
read access to the register is initiated. The data from the addressed location in the internal
register will be transferred to the Indirect Data Register. When RWB is set to logic 0, an
indirect write access to the register is initiated. The data from the Indirect Data Register will
be transferred to the addressed location in the internal register. Do not write to indirect
registers 04H to 07H.
The active high RAM busy (BUSY) bit reports if a previously initiated indirect access to the
internal register has been completed. BUSY is set to logic 1 upon writing to the Indirect
Address Register. BUSY is set to logic 0 upon completion of the RAM access. This register
should be polled to determine when new data is available in the Indirect Data Register.
1010
1011
Generator – PRBS[6:0] page
Reserved
S/UNI-2488 Telecom Standard Product Datasheet
Released
435