PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 431

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
TS1_RDI20F
TS1_FORCE_LCD
The TS1_RDI20F bits specify the configuration of RDI maintenance duration. The standard
required duration is 10 frames. The GR-253 objective duration is 20 frames. The two
options are specified by the TS1_RDI20F bit are selected as shown in Table 16.
Table 16 SIRP RDI Maintenance
The TS1_FORCE_LCD bit is used to force a Loss of ATM Cell Delineation (LCD) event. A
logic OR operation is performed on the LCD indication and the TS1_FORCE_LCD bit.
When TS1_FORCE_LCD is set high, an LCD event is assumed and RDI[1:0] is sourced
entirely from a specified 2 bit RDI code (LCD[1:0]). The TS1_FORCE_LCD bit is ignored
when TS1_RMODE[1:0] = b’01.
TS1_ERDI = 0
TS1_RDI20F
0
1
Configuration
A particular RDI value for will be maintained for the required 10 frames before
changing to a lower priority RDI code.
A particular RDI value for will be maintained for the GR-253 objective 20 frames
before changing to a lower priority RDI code.
100
100
RDI-P defect
RDI-P defect
S/UNI-2488 Telecom Standard Product Datasheet
Released
431