PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 479

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0884H: TXDLL Configuration
The DLL Configuration Register controls the basic operation of the DLL. It is not necessary to
setup this register for normal operation.
LOCK
VERN_EN
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The LOCK register is used to force the DLL to ignore phase offsets indicated by the phase
detector after phase lock has been achieved. When LOCK is set to logic zero, the DLL will
track phase offsets measured by the phase detector between the TFCLK and the feedback
clock. When LOCK is set to logic one, the DLL will not change the tap after the phase
detector indicates of zero phase offset between the TFCLK and the feedback clock for the
first time.
This bit must be set to logic 0 for normal operation.
The vernier enable register (VERN_EN) forces the DLL to ignore the phase detector and use
the tap number specified by the VERNIER[7:0] register bits. When VERN_EN is set to logic
zero, the DLL operates normally adjusting the phase offset based on the phase detector.
When VERN_EN is set to logic one, the delay line uses the tap specified by the
VERNIER[7:0] register bits.
This bit must be set to logic 0 for normal operation.
Type
R/W
R/W
R/W
R/W
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
OVERRIDE
ERRORE
VERN_EN
LOCK
Function
Unused
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
0
X
0
0
Released
479