PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 147

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
12
12.1 DS3 Frame Format
PROPRIETARY AND CONFIDENTIAL
M-subframe 1
M-subframe 2
M-subframe 3
M-subframe 4
M-subframe 5
M-subframe 6
M-subframe 7
OPERATION
The TECT3 provides support for both the C-bit parity and M23 DS3 framing
formats. The DS3 frame format is shown in Figure 27.
Figure 27: DS3 Frame Structure
X x : X-Bit Channel
P x : P-Bit Channel
M x : M-Frame Alignment Signal
· Transmit: The TECT3 inserts the FERF signal on the X-bits. FERF
· Receive: The TECT3 monitors the state and detects changes in the state
· Transmit: The TECT3 calculates the parity for the payload data over the
· Receive: The TECT3 calculates the parity for the received payload. Errors
· Transmit: The TECT3 generates the M-frame alignment signal (M1 = 0, M2
· Receive: The TECT3 finds M-frame alignment by searching for the F-bits
= 1, M3 = 0).
and the M-bits. Out-of-frame is removed if the M-bits are correct for three
consecutive M-frames while no discrepancies have occurred in the F-bits.
M-bit errors are counted in the DS3 PMON Framing Bit Error Event Count
generation is controlled by either the FERF bit of the DS3 TRAN
Configuration register or by detection of OOF, RED, LOS and AIS, as
configured by the TECT3 Master DS3 Alarm Enable register.
of the FERF signal on the X-bits.
previous M-frame and inserts it into the P1 and P2 bit positions.
are accumulated in the DS3 PMON Parity Error Event Count registers.
X 1
X 2
P 1
P 2
M 1
M 2
M 3
84 bits
F 1
F 1
F 1
F 1
F 1
F 1
F 1
84 bits
ISSUE 1
C 1
C 1
C 1
C 1
C 1
C 1
C 1
84 bits
F 2
F 2
F 2
F 2
F 2
F 2
F 2
84 bits
134
C 2
C 2
C 2
C 2
C 2
C 2
C 2
84 bits
F 3
F 3
F 3
F 3
F 3
F 3
F 3
84 bits
C 3
C 3
C 3
C 3
C 3
C 3
C 3
HIGH DENSITY T1/E1 FRAMER
84 bits
AND M13 MULTIPLEXER
PM4328 TECT3
F 4
F 4
F 4
F 4
F 4
F 4
F 4
84 bits