PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 94

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
9.24 DS3 Transmitter (DS3-TRAN)
PROPRIETARY AND CONFIDENTIAL
When an accumulation interval is signaled by a write to the PMON register
address space, the PMON transfers the current counter values into
microprocessor accessible holding registers and resets the counters to begin
accumulating error events for the next interval. The counters are reset in such a
manner that error events occurring during the reset period are not missed.
When counter data is transferred into the holding registers, an interrupt is
generated, providing the interrupt is enabled. If the holding registers have not
been read since the last interrupt, an overrun status bit is set. In addition, a
register is provided to indicate changes in the PMON counters since the last
accumulation interval.
Whenever counter data is transferred into the holding registers, an interrupt is
generated, providing the interrupt is enabled. If the holding registers have not
been read since the last interrupt, an overrun status bit is set.
The DS3 Transmitter (DS3-TRAN) Block integrates circuitry required to insert the
overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The
T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats.
When configured for the C-bit parity application, all overhead bits are inserted.
When configured for the M23 application, all overhead bits except the stuff
control bits (the C-bits) are inserted; the C-bits are inserted by the upstream
MX23 TSB.
Status signals such as far end receive failure (FERF), the alarm indication signal,
and the idle signal can be inserted when their transmission is enabled by internal
register bits. FERF can also be automatically inserted on detection of any
combination of LOS, OOF or RED, or AIS by the DS3-FRMR.
A valid pair of P-bits is automatically calculated and inserted by the DS3-TRAN.
When C-bit parity mode is selected, the path parity bits, and far end block error
(FEBE) indications are automatically inserted.
When enabled for C-bit parity operation, the FEAC channel is sourced by the
XBOC bit-oriented code transmitter. The path maintenance data link messages
are sourced by the TDPR data link transmitter.
The DS3-TRAN supports diagnostic modes in which it inserts parity or path parity
errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code
violations, or all-zeros.
ISSUE 1
81
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3