PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 226
![no-image](/images/no-image-200.jpg)
PM4328-PI
Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM4328-PI.pdf
(250 pages)
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PM4328-PI
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STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
Table 35: SBI ADD BUS Timing (Figure 84)
Notes on SBI Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up
2. When a hold time is specified between an input and a clock, the hold time is
3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
4. Maximum and minimum output propagation delays are measured with a 100
5. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the
Symbol
tS
tH
t P
t Z
SBIADD
SBIADD
SBIADD
SBIADD
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
point of the reference signal to the 1.4 Volt point of the output.
pF load on all the outputs.
reference signal to the point where the total current delivered through the
output is less than or equal to the leakage current.
Description
SREFCLK Frequency
SREFCLK Duty Cycle
All SBI ADD BUS Inputs Set-Up
Time to SREFCLK (See Note 1)
All SBI ADD BUS Inputs Hold Time
to SREFCLK (See Note 2)
SREFCLK to SAJUST_REQ Valid
(See Notes 3 and 4)
SREFCLK to SAJUST_REQ Tristate
(See Note 5)
ISSUE 1
213
Min
19.44
-50 ppm
40
4
0.75
2
2
HIGH DENSITY T1/E1 FRAMER
Max
19.44
+50 ppm
60
20
20
AND M13 MULTIPLEXER
PM4328 TECT3
Units
MHz
%
ns
ns
ns
ns
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