IDT72T36115 Integrated Device Technology, IDT72T36115 Datasheet - Page 17

• Manufacturer Part Number: IDT72T36115
• Description: 128k X 36 Terasync Fifo, 2.5v - Best Value!
• Manufacturer: Integrated Device Technology

TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
4. As well as selecting parallel programming mode, one of the default values will
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
be loaded depending on the state of FSEL0 & FSEL1.
also be loaded depending on the state of FSEL0 & FSEL1.
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
IDT72T3665,72T3675,72T3685,72T3695, 72T36105,
*LD
*LD
*LD
*LD
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
IDT72T3645, 72T3655
FSEL1
FSEL1
FSEL1
FSEL1
72T36115, 72T36125
H
H
H
H
X
X
H
H
H
H
X
X
L
L
L
L
L
L
L
L
FSEL0
FSEL0
FSEL0
FSEL0
H
H
H
H
H
H
H
H
L
L
L
L
X
X
L
L
L
L
X
X
Program Mode
Program Mode
Offsets n,m
Offsets n,m
Parallel
Parallel
Serial
Serial
1,023
255
127
255
127
511
511
63
31
15
63
31
15
7
3
7
(3)
(3)
(4)
(4)
17
PROGRAMMING FLAG OFFSETS
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
the LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on LD
during Master Reset selects serial loading of offset values. A LOW on LD during
Master Reset selects parallel loading of offset values.
the current offset values. Offset values can be read via the parallel output port
Q
not possible to read the offset values in serial fashion.
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
72T36105/72T36115/72T36125 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for PAF and PAE flags
by use of the PFM pin.
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see
Figure 25 for asynchronous PAF timing and Figure 26 for asynchronous PAE
timing.
0
-Qn, regardless of the programming mode selected (serial or parallel). It is
Full and Empty Flag offset values are user programmable. The IDT72T3645/
In addition to loading offset values into the FIFO, it is also possible to read
Figure 3, Programmable Flag Offset Programming Sequence, summaries
The offset registers may be programmed (and reprogrammed) any time
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 11, 2007