IDT72T36115 Integrated Device Technology, IDT72T36115 Datasheet - Page 20

• Manufacturer Part Number: IDT72T36115
• Description: 128k X 36 Terasync Fifo, 2.5v - Best Value!
• Manufacturer: Integrated Device Technology

NOTE:
1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
D/Q35
D/Q35
D/Q17
1st Parallel Offset Write/Read Cycle
D/Q17
2nd Parallel Offset Write/Read Cycle
D/Q16
16
IDT72T3645/55/65/75/85/95/105/115/125 ⎯ x36 Bus Width
D/Q16
IDT72T3645/55/65/75/85/95/105 ⎯
16
IDT72T3645/55/65/75/85/95/105 ⎯
16
15
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
16
15
D/Q8
D/Q8
D/Q8
D/Q8
15
14
D/Q19
18
D/Q19
18
EMPTY OFFSET (LSB) REGISTER (PAE)
15
14
13
14
FULL OFFSET (LSB) REGISTER (PAF)
17
18
17
14
13
D/Q17
13
12
D/Q17
18
16
16
8
8
13
12
Data Inputs/Outputs
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
11
12
17
16
17
16
Data Inputs/Outputs
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
12
11
EMPTY OFFSET REGISTER (PAE)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
11
10
16
15
16
15
FULL OFFSET REGISTER (PAF)
15
15
7
7
11
10
10
15
14
14
9
15
10
D/Q8
9
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
14
13
14
13
14
9
14
D/Q8
6
6
9
13
12
13
12
8
8
8
8
11
12
12
11
7
7
13
13
5
5
7
7
11
11
10
10
6
6
# of Bits Used
6
6
10
10
5
12
5
12
9
4
9
4
D/Q8
5
5
D/Q8
4
4
9
9
4
4
11
3
3
11
8
3
8
8
8
3
3
3
2
2
7
7
x18 Bus Width
7
7
# of Bits Used
# of Bits Used
2
2
x9 Bus Width
D/Q0
1
1
10
10
6
6
6
6
2
2
D/Q0
1
1
5
5
5
5
D/Q0
D/Q0
D/Q0
D/Q0
Non-Interspersed
Parity
Interspersed
Parity
1
9
1
9
4
4
4
4
3
3
3
3
2
2
2
2
D/Q0
D/Q0
1
1
1
1
Non-Interspersed
Parity
Interspersed
Parity
Non-Interspersed
Parity
Interspersed
Parity
20
D/Q17
D/Q17 D/Q16
D/Q17
D/Q17 D/Q16
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q16
D/Q16
16
16
16
15
16
15
IDT72T36115/72T36125 ⎯
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
6th Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
15
15
14
14
EMPTY OFFSET (LSB) REGISTER (PAE)
EMPTY OFFSET (MSB) REGISTER (PAE)
FULL OFFSET (LSB) REGISTER (PAF)
FULL OFFSET (MSB) REGISTER (PAF)
IDT72T36115/72T36125 ⎯
14
13
14
13
13
12
13
12
16
16
8
8
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
12
11
11
12
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
11
11
10
10
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
15
15
7
7
10
10
9
9
D/Q8
D/Q8
# of Bits Used:
10 bits for the IDT72T3645
11 bits for the IDT72T3655
12 bits for the IDT72T3665
13 bits for the IDT72T3675
14 bits for the IDT72T3685
15 bits for the IDT72T3695
16 bits for the IDT72T36105
17 bits for the IDT72T36115
18 bits for the IDT72T36125
Note: All unused bits of the
LSB & MSB are don’t care
9
9
14
14
6
6
8
8
8
8
7
7
7
7
13
13
5
5
6
6
6
6
# of Bits Used
5
5
COMMERCIAL AND INDUSTRIAL
5
5
12
12
4
4
4
4
x18 Bus Width
4
4
3
3
3
3
x9 Bus Width
11
11
3
3
2
2
18
18
18
18
2
2
D/Q0
D/Q0
D/Q0
D/Q0
TEMPERATURE RANGES
17
17
17
17
1
1
1
1
18
18
10
10
2
2
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
17
17
1
9
1
9
JANUARY 11, 2007
5907 drw07