IDT72T36115 Integrated Device Technology, IDT72T36115 Datasheet - Page 26

• Manufacturer Part Number: IDT72T36115
• Description: 128k X 36 Terasync Fifo, 2.5v - Best Value!
• Manufacturer: Integrated Device Technology

into a high impedance state. During Master or a Partial Reset the OE is the only
input that can place the output bus Qn, into High-Impedance. During Reset the
RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
READ CHIP SELECT ( RCS )
output port. When RCS goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the Low-Impedance state. When RCS goes HIGH, the next
RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master
or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only
input that provides High-Impedance control of the Qn outputs. If OE is LOW the
Qn data outputs will be Low-Impedance regardless of RCS until the first rising
edge of RCLK after a Reset is complete. Then if RCS is HIGH the data outputs
will go to High-Impedance.
the first word is written to an empty FIFO, the EF will still go from LOW to HIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of RCS. For this reason the user must take care when
a data word is written to an empty FIFO in FWFT mode. If RCS is disabled when
an empty FIFO is written into, the first word will fall through to the output register,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take RCS active LOW to access this first word, place the output bus in LOW-Z.
REN must remain disabled HIGH for at least one cycle after RCS has gone LOW.
A rising edge of RCLK with RCS and REN active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty
FIFO when RCS is HIGH. Refer to Figure 17, RCS and REN Read Operation
(FWFT Mode). The RCS pin must also be active (LOW) in order to perform
a Retransmit. See Figure 13 for Read Cycle and Read Chip Select Timing (IDT
Standard Mode). See Figure 16 for Read Cycle and Read Chip Select Timing
(First Word Fall Through Mode).
must be held active, (tied LOW). OE provides three-state control of Qn.
WRITE PORT HSTL SELECT (WHSTL)
can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master
Reset, then HSTL operation of the write port will be selected. If WHSTL is LOW
at Master Reset, then LVTTL will be selected.
READ PORT HSTL SELECT (RHSTL)
can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master
Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW
at Master Reset, then LVTTL will be selected for the read port, then echo clock
and echo read enable will not be provided.
SYSTEM HSTL SELECT (SHSTL)
HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation
of all the inputs not associated with the write and read port will be selected. If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associated with SHSTL are listed in Table 5.
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
The Read Chip Select input provides synchronous control of the Read
The RCS input does not effect the operation of the flags. For example, when
Also, when operating the FIFO in FWFT mode the first word written to an
If Asynchronous operation of the Read port has been selected, then RCS
The control inputs, data inputs and flag outputs associated with the write port
The inputs and outputs associated with the write port are listed in Table 5.
The control inputs, data inputs and flag outputs associated with the read port
The inputs and outputs associated with the read port are listed in Table 5.
All inputs not associated with the write and read port can be setup to be either
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LOAD (LD)
along with FSEL0 and FSEL1, determines one of eight default offset values for
the PAE and PAF flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset, LD
enables write operations to and read operations from the offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading
or parallel load or read of these offset values. THIS PIN MUST BE HIGH
AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO
MEMORY.
BUS-MATCHING (BM, IW, OW)
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 5 for Bus-
Matching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
HIGH on BE during Master Reset will select Little-Endian format. This function
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
mable flag timing mode. A HIGH on PFM will select Synchronous Program-
mable flag timing mode. If asynchronous PAF/PAE configuration is selected
(PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH
transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of
WCLK. Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of
WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
mode. A HIGH will select Interspersed Parity mode. The IP bit function allows
the user to select the parity bit in the word loaded into the parallel port (D
when programming the flag offsets. If Interspersed Parity mode is selected, then
the FIFO will assume that the parity bits are located in bit position D
and D
Parity mode is selected, then D
and D
Reset by the state of the IP input pin.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
During Master Reset, a LOW on IP will select Non-Interspersed Parity
This is a dual purpose pin. During Master Reset, the state of the LD input,
After Master Reset, the LD pin is used to activate the programming process
The pins BM, IW and OW are used to define the input and output bus widths.
During Master Reset, a LOW on BE will select Big-Endian operation. A
During Master Reset, a LOW on PFM will select Asynchronous Program-
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during the parallel programming of the flag offsets. If Non-Interspersed
, D
33
, D
34
and D
35
are ignored. IP mode is selected during Master
8
, D
17
COMMERCIAL AND INDUSTRIAL
and D
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TEMPERATURE RANGES
are is assumed to be valid bits
JANUARY 11, 2007
8
, D
17
0
, D
-Dn)
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