IDT72T36115 Integrated Device Technology, IDT72T36115 Datasheet - Page 38

• Manufacturer Part Number: IDT72T36115
• Description: 128k X 36 Terasync Fifo, 2.5v - Best Value!
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. LD = HIGH.
3. First data word latency = t
4. RCS is LOW.
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
Q
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
D
Q0 - Qn
D0 - Dn
WCLK
0
0
WCLK
WCS
RCLK
RCLK
rising edge of the RCLK and the rising edge of the WCLK is less than t
rising edge of WCLK and the rising edge of RCLK is less than t
WEN
SKEW1
WEN
SKEW1
RCS
REN
- D
- Q
REN
FF
EF
OE
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
ENS
t
ENS
t
ENS
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
t
RCSLZ
t
SKEW1
t
t
OLZ
ENH
SKEW1
t
REF
t
A
(1)
t
OE
+ 1*T
t
WCSS
t
ENH
t
SKEW1
RCLK
t
ENS
t
A
t
DS
1
D
(1)
+ t
NO WRITE
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
0
REF.
NO OPERATION
t
t
DH
ENH
LAST WORD
1
2
t
WFF
SKEW1
t
DS
, then EF deassertion may be delayed one extra RCLK cycle.
t
t
OHZ
t
CLKH
t
DS
SKEW1
ENS
D
, then the FF deassertion may be delayed one extra WCLK cycle.
D
X
1
NO OPERATION
t
WFF
DATA READ
t
t
t
38
ENH
WCSH
DH
t
DH
t
CLK
2
t
CLKL
t
t
CLKH
ENS
t
REF
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
t
ENS
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
COMMERCIAL AND INDUSTRIAL
t
A
2
TEMPERATURE RANGES
NEXT DATA READ
WFF
REF
t
t
ENS
t
WFF
JANUARY 11, 2007
DS
). If the time between the
). If the time between the
D
0
D
X+1
t
REF
t
t
ENH
A
5907 drw16
t
DH
5907 drw17
t
WFF
D
1