IDT72T36115 Integrated Device Technology, IDT72T36115 Datasheet - Page 32

• Manufacturer Part Number: IDT72T36115
• Description: 128k X 36 Terasync Fifo, 2.5v - Best Value!
• Manufacturer: Integrated Device Technology

JTAG INTERFACE
support the JTAG boundary scan interface. The IDT72T3645/72T3655/
72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/72T36125 in-
corporates the necessary tap controller and modified pad cells to implement the
JTAG facility.
program files for these devices.
TEST ACCESS PORT (TAP)
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
Note that IDT provides appropriate Boundary Scan Description Language
The Tap interface is a general-purpose port that provides access to the
TDO
TDI
TMS
TCLK
TRST
T
A
P
Cont-
roller
TAP
Figure 7. Boundary Scan Architecture
clkDR, ShiftDR
clklR, ShiftlR
UpdatelR
UpdateDR
Instruction Register
32
Control Signals
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
The Tap controller is a synchronous finite state machine that responds to
The Standard JTAG interface consists of four basic elements:
•
•
•
•
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Instruction Decode
Mux
5907 drw12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 11, 2007