ATA5823 ATMEL Corporation, ATA5823 Datasheet - Page 31

• Manufacturer Part Number: ATA5823
• Description: Uhf Ask/fsk Transceiver Ata5823 Ata5824
• Manufacturer: ATMEL Corporation

9.2
10. Power Supply
Figure 10-1. Power Supply
4829D–RKE–06/06
Basic Clock Cycle of the Digital Circuitry
N_PWR_ON
PWR_ON
(Command via SPI)
DVCC_OK
OFFCMD
VSINT
XTO_OK
VS1
VS2
The complete timing of the digital circuitry is derived from one clock. According to
page
divider.
T
The clock cycle of the Bit-check and the TX bit rate depends on the selected bit-rate range
(BR_Range) which is defined in control register 6 (see
is defined in control register 4 (see
by the following formulas for further reference:
BR_Range
f
DCLK
&
DCLK
• Timing of the polling circuit including bit-check
• TX bit rate
29, this clock cycle T
=
controls the following application relevant parameters:
f
---------- -
XTO
16
1
1
S R Q
0 0 no change
0 1 0
1 0 1
1 1 1
R
S
FF1
IN
Q
3.25 V typ.
V_REG
DCLK
EN
is derived from the crystal oscillator (XTO) in combination with a
OUT
Table 12-16 on page
BR_Range 0: T
BR_Range 1: T
BR_Range 2: T
BR_Range 3: T
SW_DVCC
SW_AVCC
XDCLK
XDCLK
XDCLK
XDCLK
Table 12-19 on page
40). This clock cycle T
(1.6 V typ.)
V_Monitor
ATA5823/ATA5824
= 8
= 4
= 2
= 1
T
T
T
T
DCLK
DCLK
DCLK
DCLK
DVCC_OK
(to XTO and
reset logic)
AVCC
DVCC
X
X
X
X
Lim
Lim
Lim
Lim
41) and X
XDCLK
Figure 9-2 on
is defined
Lim
which
31