ATA5823 ATMEL Corporation, ATA5823 Datasheet - Page 50

• Manufacturer Part Number: ATA5823
• Description: Uhf Ask/fsk Transceiver Ata5823 Ata5824
• Manufacturer: ATMEL Corporation

13.8
Figure 13-7. Serial Timing SCK_POL = 0, SCK_PHA = 0
50
4-wire Serial Interface
ATA5823/ATA5824
SDO_TMDO
SDI_TMDI
SCK
CS
T
SCK_setup1
X
Table 13-1.
The 4-wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial
Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received
bit by bit in synchronization with the serial clock.
Pin CS_POL defines the active level of the CS:
Table 13-2.
When CS is inactive and the transceiver is not in RX transparent mode, SDO_TMDO is in a
high-impedance state.
Pins SCK_POL and SCK_PHA defines the polarity and the phase of the serial clock SCK.
X can be either V
Command
Read TX/RX data buffer
Write TX/RX data buffer
Read control/status register
Write control register
OFF command
Delete IRQ
Not used
Not used
CS_POL
X
0
1
T
T
Out_enable
CS_setup
T
Setup
iL
Command Structure
Active Level of the CS
or V
MSB
Function
CS active high
CS active low
iH
T
Hold
MSB
T
Cycle
T
X
Out_delay
MSB
Bit 7
0
0
0
1
1
1
1
0
Bit 6
MSB-1
0
0
1
1
0
0
1
1
MSB-1
Bit 5
0
1
0
1
0
1
0
1
X
Bit 4
N4
A4
A4
X
X
X
X
X
LSB
T
SCK_setup2
Bit 3
N3
A3
A3
X
X
X
X
X
X
Bit 2
T
N2
A2
A2
T
X
X
X
X
X
SCK_hold
T
CS_disable
Out_disable
X
Bit 1
4829D–RKE–06/06
N1
A1
A1
X
X
X
X
X
Bit 0
LSB
N0
A0
A0
X
X
X
X
X