ATA5823 ATMEL Corporation, ATA5823 Datasheet - Page 54

• Manufacturer Part Number: ATA5823
• Description: Uhf Ask/fsk Transceiver Ata5823 Ata5824
• Manufacturer: ATMEL Corporation

Figure 14-1. Flow Chart RX Polling Mode/RX Mode
54
ATA5823/ATA5824
Start-up Mode:
NO
Receiving Mode:
The incomming data stream is passed via the TX/RX Data Buffer or via pin
SDO_TMDO to the connected microcontroller. If an bit error occurs the
transceiver is set back to Start-up mode.
Output level on pin RX_ACTIVE -> High
I
S
Sleep Mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic
is enabled.
Output level on Pin RX_ACTIVE -> Low; I
T
Bit-check Mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter
signal, the control bit CLK_ON and OPM0 are set to 1 and the transceiver is set
to receiving mode. Otherwise it is set to Sleep mode or to Start-up mode.
Output level on pin RX_ACTIVE -> High
I
T
S
= I
Sleep
Bit-check
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE -> High; I
T
= I
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE -> High; I
Start RX Mode
Startup_Sig_Proc
S_RX
written into the TX/RX
Startup_Sig_Proc_X
= Sleep
RX data stream is
Data Buffer
detected ?
Bit error ?
Start bit
OPM0=1
T
SLEEP
1024
?
?
YES
YES
YES
YES
=0
T
Start RX Polling Mode
DCLK
X
NO
NO
NO
Sleep
NO
NO
NO
S
= I
S
S
= I
IDLE_X
= I
and level on pin CS =
Startup_Sig_Proc_X
T_MODE = 0 AND
Set CLK_ON = 1
RX data stream
available on pin
Startup_PLL_X
Set OPM0 = 1
T_MODE = 1
P_MODE = 0
SDO_TMDO
inactive ?
Bit check
Set IRQ
ok ?
?
YES
YES
YES
;T
Startup_PLL
;
Sleep:
X
T
T
T
T
DCLK
Startup_PLL
Startup_Sig_Proc
Bit-check
Sleep
:
:
:
:
:
Defined by bits Sleep0 ... Sleep4 in Control
Register 4
Defined by bit XSleep in Control Register 4
Basic clock cycle
798.5
930
546
354
258
T
Baud0 and Baud1 in Control Register 6.
Depends on the result of the bit check.
If the bit check is ok, T
number of bits to be checked (N
on the utilized data rate.
If the bit check fails, the average time period for
range and on T
defined by bit Baud0 and Baud1 in Control
Register6.
If the transparent mode is not active and the
transceiver detects a bit error after a successful
bit check and before the start bit is detected pin
IRQ will be set to high and the transceiver is set
back to start-up mode.
Is defined by the selected bit rate range and
that check depends on the selected bit-rate
DCLK
. The bit-rate range is defined by bit
T
T
T
T
DCLK
DCLK
DCLK
DCLK
T
DCLK
(typ)
XDCLK
. The bit-rate range is
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
Bit-check
depends on the
Bit-check
) and
4829D–RKE–06/06