ATA5823 ATMEL Corporation, ATA5823 Datasheet - Page 45

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ATA5823

Manufacturer Part Number
ATA5823
Description
Uhf Ask/fsk Transceiver Ata5823 Ata5824
Manufacturer
ATMEL Corporation
Datasheet

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Figure 12-3. Timing Flow Pin N_PWR_ON, Status Bit N_Power_On
12.5
4829D–RKE–06/06
Pin PWR_ON
To switch the transceiver from OFF to IDLE mode, pin PWR_ON must set to 1 (minimum
0.8
positive edge and switches on DVCC and AVCC.
If V
sets the status bit Power_On to 1, an interrupt is issued (T
pin CLK is available.
If the level on pin PWR_ON was set to 0 before the interrupt is issued, the transceiver stays in
OFF mode.
If the transceiver is in any of the active modes (IDLE, RX, RX_Polling, TX, FD), a positive edge
on pin PWR_ON sets Power_On to 1 (after T
generates an interrupt. If Power_On is still 1 during the positive edge on pin PWR_ON, no inter-
rupt is issued. Power_On and the interrupt is deleted after reading the status register.
Start debounce counter
Stop debounce counter
RX Polling Mode or
DVCC
N_PWR_ON ?
N_PWR_ON ?
IDLE Mode or
Event on pin
Event on pin
RX Mode or
TX Mode or
FD Mode
V
T = 0
VSINT
exceeds 1.6V (typically) and the XTO is settled, the digital control logic is active and
Y
Y
) for at least T
N
N
PWR_ON
Stop debounce counter
N_Power_On = 1;
T = 8195
Pin N_PWR_ON
IRQ = 1
(see
= 0 ?
?
Y
Y
T
Figure 12-4 on page
DCLK
PWR_ON_IRQ_2
N
N
Stop debounce counter
N_Power_On = 0;
). The state transition Power_On 0
IRQ = 1
PWR_ON_IRQ_1
ATA5823/ATA5824
46). The transceiver recognizes the
) and the output clock on
45
1

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