ATA5823 ATMEL Corporation, ATA5823 Datasheet - Page 93

• Manufacturer Part Number: ATA5823
• Description: Uhf Ask/fsk Transceiver Ata5823 Ata5824
• Manufacturer: ATMEL Corporation

20. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for T
V
4829D–RKE–06/06
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
VS2
18.3
18.4
19.1
19.2
19.3
19.4
19.5
No.
19
= V
VSINT
Parameters
N_PWR_ON low to
positive edge on pin
IRQ
page
Push button debounce
time
Full-duplex Mode
Start-up PLL in
Full-duplex mode
Start-up signal
processing FD mode
Time per information Bit
in Full-duplex mode
Switch OFF Delay
Synchronization Time
= 4.4V to 5.25V (car application), typical values at V
(Figure 12-2 on
44)
Test Conditions
From OFF mode to
IDLE mode, applications
according to
on page
on page
on page 8
6-1 on page 9
XTAL:
C
C
R
battery application
C
C
C
car application
C
C
C
Every mode except OFF
mode
From IDLE mode
Data rate is fixed for
full-duplex operation
Data rate is fixed for
full-duplex operation
Time from last
transmitted bit to switch
of the power amplifier
Time after startbit
detection to begin of
payload data
transmission
m
0
m
1
3
5
1
2
5
< 2.2 pF (typ 1.8 pF)
= C
= C
= 10 nF
= C
= C
= 10 nF
< 14 fF (typ 5 fF)
120 (typ 15 )
2
4
4
3
= 68 nF
= 68 nF
= 68 nF
= 2.2 µF
6,
7,
and
Figure 4-1
Figure 5-1
amb
Figure 3-1
Figure
= –40°C to +105°C. V
29, 45
29, 45
Pin
VS1
= V
T
T
Startup_Sig_Proc_fd
T
N_PWR_ON_IRQ
VS1
VS2
Startup_PLL_fd
T
Symbol
T
Debounce
T
T
= V
BIT_fd
= V
Delay
Sync
VS2
VSINT
= V
= 3V and T
VSINT
798.5
8195
Min.
546
168
168
T
T
T
T
T
T
24
= 2.15V to 3.6V (battery application), and
DCLK
DCLK
DCLK
DCLK
DCLK
BIT-fd
amb
ATA5823/ATA5824
= 25°C unless otherwise specified.
Typ.
0.45
0.3
798.5
Max.
8195
546
168
168
T
T
T
T
T
T
0.8
1.3
24
DCLK
DCLK
DCLK
DCLK
DCLK
BIT-fd
Unit
ms
µs
µs
µs
µs
µs
µs
Type*
B
A
A
A
A
A
A
93