KSZ8862 Micrel Semiconductor, KSZ8862 Datasheet - Page 64

• Manufacturer Part Number: KSZ8862
• Description: 2-port Ethernet Switch With Non-pci Interface And Fiber Support
• Manufacturer: Micrel Semiconductor

Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR
The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment
is set, it will automatically increment the RXQ Pointer on read accesses to the data register.
The counter is incremented is by one for every byte access, by two for every word access, and by four for every double
word access.
Bank 17 QMU Data Register Low (0x08): QDRL
This register QDRL(0x08-0x09) contains the Low data word presently addressed by the pointer register. Reading maps
from the RXQ, and writing maps to the TXQ.
Bank 17 QMU Data Register High (0x0A): QDRH
This register QDRH(0x0A-0x0B) contains the High data word presently addressed by the pointer register. Reading maps
from the RXQ, and writing maps to the TXQ.
Micrel, Inc.
April 2007
Bit
15
14
13-11
10-0
Bit
15-0
Bit
15-0
Default Value
-
0x0
-
0x0
Default Value
-
Default Value
-
R/W
RO
RW
RO
RW
R/W
RW
R/W
RW
Description
Description
Description
Reserved
RXFPAI RX Frame Pointer Auto Increment
When this bit is set, the RXQ Address register increments automatically on accesses to
the data register. The increment is by one for every byte access, by two for every word
access, and by four for every double word access.
When this bit is reset, the RX frame data pointer is manually controlled by user to access
the RX frame location.
Reserved
RXFP RX Frame Pointer
RX Frame data pointer index to the Data register for access.
This field reset to next available RX frame location when RX Frame release command is
issued (through the RXQ command register).
QDRL Queue Data Register Low
This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-
directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving
words to and from the KSZ8862M regardless of whether the pointer is even, odd, or
Dword aligned. Byte, word, and Dword access can be mixed on the fly in any order. This
register along with DQRH is mapped into two consecutive word locations for 16-bit
buses, or one word location for 32-bit buses, to facilitate Dword move operations.
QDRL Queue Data Register High
This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-
directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving
words to and from the KSZ8862M regardless of whether the pointer is even, odd, or
dword aligned. Byte, word, and Dword access can be mixed on the fly in any order. This
register along with DQRL is mapped into two consecutive word locations for 16-bit
buses, or one word location for 32-bit buses, to facilitate Dword move operations.
64
KSZ8862-16/32MQL
M9999-040407-3.0