FIDO1100 Innovasic Semiconductor Inc., FIDO1100 Datasheet - Page 10

• Manufacturer Part Number: FIDO1100
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
2.1
The fido1100 core is based on the CPU32 architecture, and is compatible with the CPU32
instruction set. The fido1100 incorporates five independent hardware contexts. While all
contexts share the same Execution Unit, each of the five hardware contexts in the fido1100 has
its own register set, execution priority and exception vector table. From an application’s view,
this unique feature of the fido1100 allows it to operate as five independent machines in one:
2.2
The fido1100 is fully compliant with the IEEE 1149.1 Test Access Port and Boundary-Scan
architecture (see Table 2). The fido1100 architecture is equipped with the TAP (Test Access
Port) interface, TAP controller, instruction register, instruction decoder, boundary-scan register,
and by-pass register.
JTAG emulation and debug interface
Available in a 208-pin PQFP, BGA 10- by 10-mm package, and BGA 15- by 15-mm
package
3.3V operation with 5V-tolerant I/O
Industrial temperature grade
Software development supported by libraries and tools including UIC firmware for
various interface protocols and formats, as well as a customized GNU tool set.
Core CPU
32-bit address and data paths on-chip
66-MHz operation
Instruction execution from external memory or fast internal memory.
Each hardware context has its own copy of:
– Eight 32-bit User Data Registers (D0-D7)
– Seven 32-bit Address Registers (A0-A6)
– Two 32-bit Stack Pointers (A7 and A7')
– One 32-bit Program Counter
– One 16-bit Status Register (SR)
– One 32-bit Vector Base Register (VBR)
JTAG
®
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April 15, 2010
Data Sheet
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