MG74K Oki Semiconductor, MG74K Datasheet - Page 13

• Manufacturer Part Number: MG74K
• Description: 0.15?m Customer Structured Array
• Manufacturer: Oki Semiconductor

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Macrocells for Driving Clock Trees
Oki offers the clock tree synthesis (CTPKS) in the Cadence Design Systems, Inc. Physically Knowledge-
able Synthesis (PKS) tool. CTPKS constructs buffer trees for any number of specified clocks in a design.
CTPKS builds these clock trees one by one, then explores the different tree structures. For each structure,
CTPKS places new buffers or inverters and groups the clock leaf pins into clusters so that the pin and
wire loads are balanced. PKS timing verification is run on the newly created clock tree, with parasitics
extracted from the location of each buffer and inverter. If the performance of the clock tree is better than
that of the previous one, the new tree is kept. Otherwise it is rejected.
CTPKS uses the following predefined priority of constraints when selecting the best clock tree topology:
After finding the best topology according to the priority list above, CTPKS satisfies the minimum delay
constraint by adding appropriate padding buffers.
1. Satisfy the maximum load and maximum transition delay constraints.
2. Satisfy the maximum delay constraint.
3. Satisfy the maximum skew constraint.
4. Minimize the size of the clock tree.
Oki Semiconductor
MG74K/75K/76K
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