MG74K Oki Semiconductor, MG74K Datasheet - Page 15

• Manufacturer Part Number: MG74K
• Description: 0.15?m Customer Structured Array
• Manufacturer: Oki Semiconductor

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DESIGN PROCESS
The following figure illustrates the overall IC design process, also indicating the three main interface
points between external design houses and Oki ASIC Application Engineering.
[1] Oki’s Circuit Data Check program (CDC) verifies logic design rules
[2] Oki’s Test Data Check program (TDC) verifies test vector rules
[3] Oki’s Test Pattern Language (TPL)
[4] Alternate Customer-Oki design interfaces available in addition to standard level 2
[5] Requires Synopsys timing script for Oki timing driven layout
Synopsys Timing Script
Manufacturing
Prototype
(optional)
Scan Insertion (Optional)
Signal Integrity Analysis
Post-Layout Simulation
Static Timing Analysis
Scan and Boundary
Netlist Conversion
Physical Design
Floorplanning
(optional)
(EDIF 200)
CDC
[1]
[5]
Test Program
Conversion
VHDL/Verilog HDL Description
Synthesis/Power Synthesis
Gate-Level Simulation and
Formal Verification and
Check/Formal Verification)
Verification (Design Rule
Static Timing Analysis
Pre-Layout Simulation
Intent Verification
Formal Verification
Floorplanning
Figure 5. Oki’s Design Process
Test Vector Conversion
Functional Test Vectors
Pattern Generation
Automatic Test
Fault Simulation
(Oki TPL
TDC
[2]
[3]
)
Level 1
Level 2
Level 2.5
Level 3
Oki Semiconductor
[4]
[4]
[4]
MG74K/75K/76K
Oki Interface
CAE Front-End
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