MG74K Oki Semiconductor, MG74K Datasheet - Page 16

• Manufacturer Part Number: MG74K
• Description: 0.15?m Customer Structured Array
• Manufacturer: Oki Semiconductor

Automatic Test Pattern Generation
Oki’s 0.15µm ASIC technologies support ATPG using full scan-path design techniques, including the fol-
lowing:
ATPG methodology is described in detail in Oki’s Scan Path Application Note.
Floorplanning Design Flow
Oki offers the floorplanning tool (OKI FP) for high-density ASIC design. The three main purposes for
Oki’s floorplanning tool is to:
In a traditional design approach with synthesis tools there is no physical cluster information provided in
the synthesis tool, and so it is difficult to synthesize logic using predicted interconnection delay due to
wire length. Synthesis tools may therefore create an over-optimized or under-optimized result.
Floorplanning allows designers to estimate and control parasitic capacitance in a circuit by participating
in the physical design process. Designers can partition their ASIC circuit in the most efficient hierarchical
manner, and/or specify the exact placement of critical timing paths to guarantee high-speed perfor-
mance.
Floorplanning also allows the reduction of layout iterations, minimizing a design’s overall TAT. As par-
asitic capacitance dominates a circuit’s timing in sub-micron technologies, an accurate capacitance esti-
mation is crucial for accurate pre-layout timing simulation. Quite often, designers have to iterate the
circuit layout because unexpected post-layout capacitance causes unacceptable circuit performance.
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• High fault coverage
• Uses Synopsys DFT Compiler and Tetramax
• Automatically inserts scan structures
• Connects scan chains
• Traces and reports scan chains
• Checks for rule violations
• Generates complete fault reports
• Allows multiple scan chains
• Supports test point insertion and vector compaction
• Ensure conformance of critical circuit performance specifications
• Shorten overall design TAT
• Hierarchical Layout
MG74K/75K/76K
Oki Semiconductor
Scan Data In
Scan Select
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Figure 6. Full Scan Path Configuration
D
SD
SS
C
FD1AS
QN
Q
Combinational Logic
A
B
D
SD
SS
C
FD1AS
QN
Q
Scan Data Out