MG74K Oki Semiconductor, MG74K Datasheet - Page 6

• Manufacturer Part Number: MG74K
• Description: 0.15?m Customer Structured Array
• Manufacturer: Oki Semiconductor

MG74K/75K/76K CSA Layout Methodology
The procedure to design, place, and route a CSA is as follows.
Figure 2 shows a base array after placement of the optimized memory macrocells.
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1. Select suitable base array frame from the available predefined sizes. To select a base array size:
2. Make a floor plan for the design’s megacells.
3. Place and route logic into the array transistors.
MG74K/75K/76K
- Identify macrocell functions required and minimum array size to hold macrocell functions.
- Add together all the area occupied by the required random logic and macrocells and select
- Oki Design Center engineers verify the master slice and review simulation.
- Oki Design Center or customer engineers floorplan the array using Oki’s supported floor-
- Using Oki CAD software, Design Center engineers remove the SOG transistors and replace
- Oki Design Center engineers use layout software and customer performance specifications
Oki Semiconductor
the optimum array.
planner or Cadence DP3 and customer performance specifications.
them with diffused memory macrocells to the customer’s specifications.
to connect the random logic and optimized memory macrocells.
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Figure 2. Optimized Memory Macrocell Floor Plan
Mega macrocells (Standard Cell block)
High-density RAM