MBM29DL16XTE70PFTN Meet Spansion Inc., MBM29DL16XTE70PFTN Datasheet - Page 41

• Manufacturer Part Number: MBM29DL16XTE70PFTN
• Description: Flash Memory Cmos 16m 2m ? 8/1m ? 16 Bit Dual Operation
• Manufacturer: Meet Spansion Inc.

• DQ
Sector Erase Timer
• DQ
Toggle Bit II
• Reading Toggle Bits DQ
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
be used to determine if the sector erase timer window is still open. If DQ
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
the second status check, the command may not have been accepted.
See “Hardware Sequence Flags Table”.
This toggle bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
address of the non-erase suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows:
For example, DQ
(DQ
DIAGRAM.
Furthermore, DQ
mode, DQ
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Whenever the system initially begins reading toggle bit status, it must read DQ
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
3
2
2
6
2
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
is different from DQ
toggles while DQ
2
toggles if this bit is read from an erasing sector.
2
2
and DQ
can also be used to determine which sector is being erased. When the device is in the erase
7
6
3
to DQ
does not.) See also “Toggle Bit Status Table” and “(9) DQ
6
prior to and following each subsequent Sector Erase command. If DQ
2
/DQ
in that DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
2
0
on the following read cycle.
6
, can be used to determine whether the devices are in the Embedded Erase
6
Retired Product DS05-20874-8E_July 12, 2007
toggles only when the standard program or Erase, or Erase Suspend
5
is high (see the section on DQ
2
to toggle during the Embedded Erase Algorithm. If the
MBM29DL16XTD/BD
5
through successive read cycles, deter-
3
3
is high (“1”) the internally controlled
is low (“0”), the device will accept
5
) . If it is, the system should then
2
bit.
7
to DQ
2
vs. DQ
0
at least twice in a row
6
” in ■TIMING
7
, is summarized
3
were high on
5
has not
-70/90
3
may
3
will
5
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