MBM29DL16XTE70PFTN Meet Spansion Inc., MBM29DL16XTE70PFTN Datasheet - Page 42

• Manufacturer Part Number: MBM29DL16XTE70PFTN
• Description: Flash Memory Cmos 16m 2m ? 8/1m ? 16 Bit Dual Operation
• Manufacturer: Meet Spansion Inc.

42
MBM29DL16XTD/BD
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ
*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ
• RY/BY
Ready/Busy
• Byte/Word Configuration
• Data Protection
Program
Erase
Erase-Suspend Read
(Erase-Suspended Sector)
Erase-Suspend Program
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status
of the operation. (Refer to “(4) Toggle Bit Algorithm” in “■ FLOW CHART”.)
The MBM29DL16XTD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL16XTD/BD are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to “(10) RY/BY Timing Diagram during Program/Erase
Operations” and “(11) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram.
The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
be connected to the host system via more than one RY/BY pin in parallel.
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL16XTD/BD devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to “(12) Timing Diagram for Word Mode Configuration” and “(13) Timing Diagram for Byte Mode Configuration”
and “(14) BYTE Timing Diagram for Write Operations” in ■TIMING DIAGRAM for the timing diagram.
The MBM29DL16XTD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
Mode
Retired Product DS05-20874-8E_July 12, 2007
8
to DQ
Toggle Bit Status Table
-70/90
DQ
DQ
DQ
0
1
14
7
7
7
bits are tri-stated. However, the command bus cycle is always
0
to DQ
7
and the DQ
Toggle
Toggle
Toggle
DQ
1
6
2
to toggle.
8
to DQ
CC
; multiples of devices may
2
15
bit.
bits are ignored. Refer
Toggle*
Toggle
DQ
1*
1
CC
2
2
power-up
1
15
/A
-1
pin
0