CS2411 Amphion, CS2411 Datasheet - Page 5

• Manufacturer Part Number: CS2411
• Description: User-programmable Fft/ifft 1024-point Block Based
• Manufacturer: Amphion

Table 6 gives the simulation results on the transform accuracy
of CS2411 core. These results are obtained by applying 64
blocks of 13-bit random input data to the core and the scaling
down control is set such that there is just no overflow in the
computation. For example, the output magnitude is
maximized while no overflow occurs. The 13-bit output data
from the core is compared with the result of double precision
FFT model. The error is measured in terms of the output LSB
weight. It is noted that when overflow occurs the transform
accuracy will be decreased severely.
Figure 4: Word Length In Arithmetic Operations
Loading the input data is performed under the control of XBS
signal. The XBS signal should be asserted when the output
signal XBIP and BUSY are LOW. It indicates the first data of
the 1024-point data block. The data is clocked in on the clock
rising edge. The remaining data of the 1024-point data block is
loaded in on the rising edge of the clock in natural order
successively.
When the core starts to load a 1024-point data block, signals
XBIP and BUSY are asserted to indicate that loading of a data
13 bits
LOADING INPUT AND DOWNLOADING
Transform Size
SDC setting
Scaling Factor
Number of complex data
samples compared
Maximal output Magnitude
Maximal Error (Re)
Maximal Error (Imag)
Average Absolute Output
Average Absolute Error
Mean Square Error
Average SNR
Table 6: Simulation Results of Transform Accuracy
Butterfly
Radix-4
15 bits
Multiply
13 bits
twiddle
RESULT
16 bits
Butterfly
Radix-4
17 bits
1024-point
54.876 dB
0.851654
472.134
1/(2^7)
1.3474
2624
64K
3
7
7
Overflow
Round
Detect
Shift
13 bits
block is in progress. Signal XBS will be ignored when XBIP is
HIGH. When the last data of the block is loaded into the core,
XBIP signal returns to LOW and signal BUSY stays HIGH to
indicate the transform computation is in progress. Signal XBS
is still ignored in this case until Busy returns to LOW.
The CS2411 core starts the transform prior to the completion
of loading the 1024-point data block when the required data
has been loaded, i.e., the input data loading is overlapped
with the first computation pass. This compensates the latency
introduced by the pipelined computation units so that the
input data loading and the four computation passes can be
completed in 5*1024 clock cycles. Signal Done goes to HIGH
when the transform result is available (after 5093 cycles).
Downloading of the transform result is started by asserting
the input signal YEnab when Done is HIGH. Signal Done
returns to LOW when downloading is started. The first
sample of the transform result comes out from the core in the
natural order two clock cycles later after YEnab is asserted.
Output signal YAV is asserted when the data on port YRe and
YIm are valid and output signal YBS is asserted when the first
sample of the 1024-point result is on the output port. The
output data burst out from the core in 1024 clock cycles.
Downloading the result can be overlapped with the 4th
computation pass to achieve 5*1024 clock cycles operation, if
input signal YEnab is asserted as soon as the output signal
Done goes to HIGH. The loading of the next data block can be
started as soon as output signal Busy is de-asserted. Figure 5
shows the functional timing for the 5*1024 clock cycle I/O and
transform operation. It is noted that the input signal YEnab
can be constantly asserted and if so the transform result will
be automatically downloaded when available.
It should be noted that the core waits for YEnab being asserted
when signal Done goes HIGH to start the downloading
process, allowing the user to control the transform data flow.
The system clock rate is not restricted to the 5*1024 cycles and
can be any rate higher than 5X the data rate. In this case if the
downloading result has been completed but loading the next
block is not started, signal Done will go to HIGH again to
indicate that the transform result is still available in the
internal memory and can be downloaded again. This feature
can be utilized in C-OFDM modulation systems to perform
the guard interval insertion. Figure 6 shows the operating
flowchart for the CS2411 core.
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