CS3710 Amphion, CS3710 Datasheet - Page 3

• Manufacturer Part Number: CS3710
• Description: 32 Qam Modulator
• Manufacturer: Amphion

Each sub-block function in Figure 3 is described in this
section. The CS3710 has two clock signals, namely,
TXUSRCLK and CLK. These two clocks are linked by the
symbol rate, which is 120/63 or 12/7 times TXUSRCLK. The
Input data stream is block based and synchronised by
TXUSRCLK with each block containing 224 bytes. The output
stream consists of the shaped and filtered I and Q samples and
TCM_I and TCM_Q symbols synchronised by CLK.
Functions of the PRBS sub-block are:
•
•
Input data TXDATA and RXDATA (loopback mode) are
registered using the TXUSRCLK. The data is multiplexed to
feed BlkSync according to the configuration of the Core. When
TXRX is High, and PRBS is low, the TXDATA is selected,
otherwise if the PRBS is High, the PRBS sequence is selected.
In all cases, the SSB data is generated if SSB is High.
TWOSCOM
MODULATOR LOOP BACK INPUT
RXDATA[7:0]
RXSYNC
MODULATOR OUTPUT INTERFACE
TXI_OUT[9:0]
TXQ_OUT[9:0]
TX_Valid
TXFULL
TXEMPTY
TCM_I[4:0]
TCM_Q[4:0]
TCM_Valid
Register input data TXDATA, RXDATA and all control
signals
Multiplex input data according to input control pin
configuration
Name
SYSTEM CLOCKS
Table 1: CS3710 32 QAM Modulator Interface Signal Descriptions
PRBS
O
O
O
O
O
O
O
O
I/O
I
I
I
FUNCTIONAL OPERATION
Output Format: 1: 2’s complement, 0: Offset binary
Byte wide loop back data input
Indicates first byte in Frame – asserted during the TXUSRCLK cycle before the
first byte of a frame is on the loop back RXDATA port
Output symbol data to I-rail DAC – clocked out on the rising edge of CLK
Output symbol data to Q-rail DAC – clocked out on the rising edge of CLK
Output data valid indicator signal
Mapper FIFO full indicator
Mapper FIFO empty indicator
Output TCM/QAM32 symbol data to I-rail– clocked out on the rising edge of CLK
Output TCM/QAM32 symbol data to Q-rail– clocked out on the rising edge of CLK
Output TCM/QAM32 symbol valid indicator signal
Maximal-length 20 bit scrambler, generating 2
which follows the IntelSat IESS-308 standard. Generator
polynomial used is:
There is one cycle delay in this module.
The Reed-Solomon encoding algorithm is implemented
according to following parameters:
• Galois field GF(
• Primitive polynomial:
• Generator polynomial:
The RS encoder supports codewords of the format (240,224).
The 16 parity symbols calculated by the RS encoder are added
to the end of the information bytes that were input. The start
of frame sync flag is also piped through with the same latency
as the data to be fed onto the next module in the chain.
REED SOLOMON ENCODER
p X
Description
=
1
2
+
8
SCRAMBLER
X
).
3
+
X
g X
20
m X
=
=
X
1
+
+
X
0
2
+
X
X
+
3
+
1
X
... X
4
+
20
X
-1 patterns,
+
8
2T 1
–
3
TM