MB81ES171625 Fujitsu Media Devices Limited, MB81ES171625 Datasheet - Page 16

• Manufacturer Part Number: MB81ES171625
• Description: SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP
• Manufacturer: Fujitsu Media Devices Limited

16
MB81ES171625/173225-15-X
1. SDR I/F FCRAM Basic Function
2. FCRAM
3. Clock (CLK) and Clock Enable (CKE)
4. Chip Select (XCS)
5. Command Input (
6. Address Input (A
FUNCTIONAL DESCRIPTION
Three major differences between SDR I/F FCRAMs and conventional DRAMs are : synchronized operation,
burst mode, and mode register.
The synchronized operation is the fundamental difference. SDR I/F FCRAM uses a clock input for synchroni-
zation, while DRAM is basically asynchronous memory although it has been using two clocks, XRAS and XCAS.
Each operation of DRAM is determined by their timing phase differences while each operation of SDR I/F FCRAM
is determined by commands and all operations are referenced to a rising edge of a clock.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a
column address for the first access is set, following addresses are automatically generated by the internal column
address counter.
The mode register is to configure SDR I/F FCRAM operation and function into desired system conditions.
“ MODE REGISTER TABLE” shows how SDR I/F FCRAM can be configured for system requirements by mode
register programming.
The program to the mode resister should be excuted after all banks are precharged.
MB81ES171625/173225 utilizes FCRAM core technology. FCRAM is an acronym for Fast Cycle Random Access
Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
All input and output signals of SDR I/F FCRAM use register type buffers. CLK is used as a trigger for the register
and internal burst counter increment. All inputs are latched by a rising edge of CLK. All outputs are validated by
a rising edge of CLK. CKE is a high active clock enable signal. When CKE
during active cycle, the next clock will be internally masked. During idle state (all banks have been
precharged) , the Power Down mode (standby) is entered with CKE
standby current.
XCS enables all command inputs, XRAS, XCAS, XWE and address inputs. When XCS is High, command signals
are negated but internal operations such as a burst cycle will not be suspended. If such a control isn’t needed,
XCS can be tied to ground level.
Unlike a conventional DRAM, XRAS, XCAS and XWE do not directly imply SDR I/F FCRAM operations, such
as Row address strobe by XRAS. Instead, each combination of XRAS, XCAS, and XWE input in conjunction
with XCS input at the rising edge of the CLK determines SDR I/F FCRAM operations. Refer to “ FUNCTIONAL
TRUTH TABLE.”
Address input selects an arbitrary location of each memory cell matrix, 524,288 ( 16 bit) or 262,144 ( 32 bit) .
A total of 19 (
6 bit ( 16 bit) or 5 bit ( 32 bit) column addresses matrix. SDR I/F FCRAM adopts an address multiplexer in order
to reduce the pin count of the address line. At a Bank Active command (ACTV) , 13 bit Row addresses are
initially latched and the remainder of 6 bit (
Column address strobe command of either a Read command (READ or READA) or a Write command (WRIT
or WRITA) . A
TM
10
16 bit) or 18 (
selects READ or READA, WRIT or WRITA and PRE or PALL.
12
XRAS
to A
,
0
)
XCAS
32 bit) address input signals are required to decode 13 bit Row addresses and
and XWE)
16 bit) or 5 bit (
32 bit) Column addresses are then latched by a
Low and this will make extremely low
Low is latched at a clock input